The subject of the present invention is a delay circuit with adjustable delay employing a switching flip-flop.
According to the prior art, such a circuit employs a D-type flip-flop associated with a clock. The delay is determined by a resistance-capacitance product RC, which makes it difficult to obtain a variable delay in an integrated circuit.
The patents U.S. Pat. Nos. 4,795,923 and 4,862,020 describe integratable delay circuits whose delay is continuously adjustable with the aid of a variable voltage. These circuits require several differential stages, the outputs of which are coupled, hence resulting in relatively complicated circuits. The subject of the present invention is a circuit of the type mentioned in the first paragraph and whose delay is continuously adjustable as well as being simple to employ.